1. Field of the Invention
The embodiments discussed herein relate to a silicon carbide semiconductor device and a method of manufacturing a silicon carbide semiconductor device.
2. Description of the Related Art
Silicon carbide (SiC) has high critical field strength and has been attracting attention as an optimal semiconductor material in low-loss power devices. An oxide film (SiO2 film) may be formed by thermal oxidation on a semiconductor substrate using silicon carbide (hereinafter, silicon carbide substrate) and therefore, the development of power metal oxide semiconductor field effect transistors (MOSFETs) using an oxide film formed by thermal oxidation as a gate insulating film is advancing (for example, refer to Japanese Laid-Open Patent Publication No. 2012-129503).
At an interface of a silicon carbide substrate (hereinafter, SiO2/SiC interface) and an oxide film formed by thermal oxidation, the interface state density (Dit) is high, the channel mobility decreases, and the ON-resistance increases. Therefore, methods of reducing the interface state density Dit of the SiO2/SiC interface by forming an oxide film on a silicon carbide substrate by thermal oxidation in a nitrous oxide (N2O) gas atmosphere or a nitric oxide (NO) gas atmosphere are being developed.
Formation of an oxide film that becomes a gate insulating film by thermal oxidation in a nitrous oxide or a nitric oxide gas atmosphere enables the interface state density Dit of the SiO2/SiC interface to be made 2×1012cm−2·eV−1 or less and enables realization of high channel mobility. Therefore, in a MOSFET using silicon carbide (hereinafter, SiC-MOSFET), it is possible to form a metal oxide semiconductor (MOS) gate (an insulated gate of a metal oxide semiconductor) structure that uses a good quality oxide film as a gate insulating film.
A traditional method of manufacturing a silicon carbide semiconductor device will be described taking a SiC-vertical MOSFET of a planar gate structure as an example. FIG. 6 is a cross-sectional view of an example of a silicon carbide semiconductor device manufactured by a traditional method of manufacturing a silicon carbide semiconductor device. First, on a front surface of an n+-type silicon carbide substrate 101 that becomes an n+-type drain region, an n−-type silicon carbide layer 121 that becomes an n−-type drift region 102 is formed by epitaxial growth. Next, p-type base regions 103 are selectively formed in a surface layer of the n−-type silicon carbide layer 121 by ion implantation of a p-type impurity.
On the n−-type silicon carbide layer 121, a p−-type silicon carbide layer 122 that becomes a p−-type base region 104 is formed by epitaxial growth. By the processes up to here, a silicon carbide base 120 constituted by the n+-type silicon carbide substrate 101 and the silicon carbide layers 121, 122 is formed. Next, n-type regions 107 penetrating the p−-type silicon carbide layer 122 in a depth direction are selectively formed by ion implantation. Subsequently, n+-type source regions 106 and p+-type contact regions 105 are selectively formed in the p−-type silicon carbide layer 122 by ion implantation.
Heat treatment for activating the regions formed by ion implantation (hereinafter, activation annealing) is performed. Next, a gate insulating film 108 is formed by thermal oxidation in a nitrous oxide atmosphere. On the gate insulating film 108, a poly-silicon (poly-Si) layer that becomes a gate electrode 109 is formed. The poly-silicon layer is patterned and a portion covering from a portion of the p−-type base region 104 between the n+-type source region 106 and the n-type region 107 to the n-type region 107 is left. Next, an interlayer insulating film 110 is formed so as to cover the gate electrode 109.
Next, a nickel silicide film that becomes a source contact portion (electrically contacting portion) 111 contacting the p+-type contact regions 105 and the n+-type source regions 106 is formed, and a silicon carbide portion and the source contact portions 111 are caused to form an ohmic contact. On the entire base front surface, an aluminum wiring layer 112 that becomes a source electrode contacting the source contact portion 111 is formed to a thickness of 5 μm. A polyimide layer that becomes a passivation protective film 113 is formed on the aluminum wiring layer 112 and is hardened (cured). Thereafter, a drain electrode 114 is formed on a rear surface of the silicon carbide base 120 whereby the SiC-MOSFET depicted in FIG. 6 is completed.
Further, use of an oxide film that uses N2O.NO gas enables realization of high channel mobility where the interface state density is 2×1012cm−2·eV−1 or less, which has come to be considered a good quality structure as a gate insulating film of a SiC-MOSFET.
For example, as methods of forming wiring on the substrate of a semiconductor device, a technique of forming an aluminum (Al) material on a base of titanium (Ti) (for example, refer to Japanese Laid-Open Patent Publication No. H7-176615), a technique of having an alloy layer in a metal wiring layer of a pad, etc. (for example, refer to Japanese Laid-Open Patent Publication No. 2003-309124), and a technique of providing a barrier metal layer that suppresses the diffusion of aluminum between the source electrode and the interlayer insulating film, and between the gate pad and the gate electrode (for example, refer to Japanese Laid-Open Patent Publication No. 2012-129503) have been disclosed.